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Highly Dependable Many-Core SoCs by Embedded Instrumentation

This research  work describes the usage of embedded instruments, which provide (periodic) data to be employed for predicting the remaining lifetime of processor cores in homogeneous multi- processor SoCs during their lifetime. This forms the basis of self-repair with no mean down time for these SoCs and dramatically  improving their dependability. We accomplish this goal by optimally choosing and combining our designed EI, such as delay and current monitors to provide non-redundant measurement data. Accelerated stress tests were carried out using a set of processor cores in combination with a number of health monitors providing historic data. These results form the basis of a remaining lifetime prediction model for delay (processor clock frequency), After the final test of an individual SoC, these stored coefficients can be periodically updated in an embedded processor during its lifetime by the EI . In the case of seriously degrading cores, counteractions are automatically taken, like core isolation and (e.g. spare)  replacement. The result is a zero mean downtime SoC with dramatic reliability improvement in our 9 processor-core SoC.